Nanoscale VLSI

Devices, Circuits and Applications

Author: Rohit Dhiman

Publisher: Springer

ISBN:

Category: Technology & Engineering

Page: 319

View: 339

This book describes methodologies in the design of VLSI devices, circuits and their applications at nanoscale levels. The book begins with a discussion on the dominant role of power in highly scaled devices and circuits. The 15 chapters of the book are classified under four sections that cover design, modeling, and simulation of electronic, magnetic and compound semiconductors for their applications in VLSI devices, circuits, and systems. This comprehensive volume eloquently presents the design methodologies for ultra–low power VLSI design, potential post–CMOS devices and circuits, and their applications from the architectural and system perspective. The book shall serve as an invaluable reference book for the graduate students, Ph.D./ M.S./ M.Tech. Scholars, researchers, and practicing engineers working in the frontier areas of nanoscale VLSI design.

Nanoscale VLSI

Devices, Circuits and Applications

Author: Rohit Dhiman

Publisher: Springer Nature

ISBN:

Category: Technology & Engineering

Page: 319

View: 988

This book describes methodologies in the design of VLSI devices, circuits and their applications at nanoscale levels. The book begins with the discussion on the dominant role of power dissipation in highly scaled devices.The 15 Chapters of the book are classified under four sections that cover design, modeling, and simulation of electronic, magnetic and compound semiconductors for their applications in VLSI devices, circuits, and systems. This comprehensive volume eloquently presents the design methodologies for ultra–low power VLSI design, potential post–CMOS devices, and their applications from the architectural and system perspectives. The book shall serve as an invaluable reference book for the graduate students, Ph.D./ M.S./ M.Tech. Scholars, researchers, and practicing engineers working in the frontier areas of nanoscale VLSI design.

Mitigation of Soft Errors in Nanoscale VLSI Circuits

Author: Nagarajan Ranganathan

Publisher: Springer

ISBN:

Category: Technology & Engineering

Page: 200

View: 896

Reliability is a key concern in VLSI systems and transient/intermittent faults, often caused by soft errors, require designers to create special mitigation techniques. This book describes such techniques, spanning all levels of the design flow, to reduce systematically the vulnerability of VLSI systems to soft errors. Readers will be enabled to address soft error issues early in their design flow, allowing them to weigh the implications of dedicating more resources for soft error detection and prevention, against the correlating impact on delay, power and area.

Architectures and Algorithms for Mitigation of Soft Errors in Nanoscale VLSI Circuits

Author: Koustav Bhattacharya

Publisher:

ISBN:

Category:

Page:

View: 994

ABSTRACT: The occurrence of transient faults like soft errors in computer circuits poses a significant challenge to the reliability of computer systems. Soft error, which occurs when the energetic neutrons coming from space or the alpha particles arising out of packaging materials hit the transistors, may manifest themselves as a bit flip in the memory element or as a transient glitch generated at any internal node of combinational logic, which may subsequently propagate to and be captured in a latch. Although the problem of soft errors was earlier only a concern for space applications, aggressive technology scaling trends have exacerbated the problem to modern VLSI systems even for terrestrial applications. In this dissertation, we explore techniques at all levels of the design flow to reduce the vulnerability of VLSI systems against soft errors without compromising on other design metrics like delay, area and power. We propose new models for estimating soft errors for storage structures and combinational logic. While soft errors in caches are estimated using the vulnerability metric, soft errors in logic circuits are estimated using two new metrics called the glitch enabling probability (GEP) and the cumulative probability of observability (CPO). These metrics, based on signal probabilities of nets, accurately model soft errors in radiation-aware synthesis algorithms and helps in efficient exploration of the design solution space during optimization. At the physical design level, we leverage the use of larger netlengths to provide larger RC ladders for effectively filtering out the transient glitches. Towards this, a new heuristic has been developed to selectively assign larger wirelengths to certain critical nets. This reduces the delay and area overhead while improving the immunity to soft errors. Based on this, we propose two placement algorithms based on simulated annealing and quadratic programming which significantly reduce the soft error rates of circuits. At the circuit level, we develop techniques for hardening circuit nodes using a novel radiation jammer technique. The proposed technique is based on the principles of a RC differentiator and is used to isolate the driven cell from the driving cell which is being hit by a radiation strike. Since the blind insertion of radiation blocker cells on all circuit nodes is expensive, candidate nodes are selected for insertion of these cells using a new metric called the probability of radiation blocker circuit insertion (PRI). We investigate a gate sizing algorithm, at the logic level, in which we simultaneously optimize both the soft error rate (SER) and the crosstalk noise besides the power and performance of circuits while considering the effect of process variations. The reliability centric gate sizing technique has been formulated as a mathematical program and is efficiently solved. At the architectural level, we develop solutions for the correction of multi-bit errors in large L2 caches by controlling or mining the redundancy in the memory hierarchy and methods to increase the amount of redundancy in the memory hierarchy by employing a redundancy-based replacement policy, in which the amount of redundancy is controlled using a user defined redundancy threshold. The novel architectures and the new reliability-centric synthesis algorithms proposed for the various design abstraction levels have been shown to achieve significant reduction of soft error rates in current nanometer circuits. The design techniques, algorithms and architectures can be integrated into existing design flows. A VLSI system implementation can leverage on the architectural solutions for the reliability of the caches while the custom hardware synthesized for the VLSI system can be protected against radiation strikes by utilizing the circuit level, logic level and layout level optimization algorithms that have been developed.

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits

Author: Saraju P. Mohanty

Publisher: Springer Science & Business Media

ISBN:

Category: Technology & Engineering

Page: 302

View: 504

This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.

VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability

24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers

Author: Thomas Hollstein

Publisher: Springer

ISBN:

Category: Computers

Page: 233

View: 188

This book contains extended and revised versions of the best papers presented at the 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, held in Tallinn, Estonia, in September 2016. The 11 papers included in the book were carefully reviewed and selected from the 36 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the latest scientific and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) Design.

Nanoscale CMOS VLSI Circuits: Design for Manufacturability

Author: Sandip Kundu

Publisher: McGraw Hill Professional

ISBN:

Category: Technology & Engineering

Page: 316

View: 851

Cutting-Edge CMOS VLSI Design for Manufacturability Techniques This detailed guide offers proven methods for optimizing circuit designs to increase the yield, reliability, and manufacturability of products and mitigate defects and failure. Covering the latest devices, technologies, and processes, Nanoscale CMOS VLSI Circuits: Design for Manufacturability focuses on delivering higher performance and lower power consumption. Costs, constraints, and computational efficiencies are also discussed in the practical resource. Nanoscale CMOS VLSI Circuits covers: Current trends in CMOS VLSI design Semiconductor manufacturing technologies Photolithography Process and device variability: analyses and modeling Manufacturing-Aware Physical Design Closure Metrology, manufacturing defects, and defect extraction Defect impact modeling and yield improvement techniques Physical design and reliability DFM tools and methodologies

Nanoscale CMOS VLSI Circuits: Design for Manufacturability

Author: Sandip Kundu

Publisher: McGraw-Hill Education

ISBN:

Category: Technology & Engineering

Page: 316

View: 188

Cutting-Edge CMOS VLSI Design for Manufacturability Techniques This detailed guide offers proven methods for optimizing circuit designs to increase the yield, reliability, and manufacturability of products and mitigate defects and failure. Covering the latest devices, technologies, and processes, Nanoscale CMOS VLSI Circuits: Design for Manufacturability focuses on delivering higher performance and lower power consumption. Costs, constraints, and computational efficiencies are also discussed in the practical resource. Nanoscale CMOS VLSI Circuits covers: Current trends in CMOS VLSI design Semiconductor manufacturing technologies Photolithography Process and device variability: analyses and modeling Manufacturing-Aware Physical Design Closure Metrology, manufacturing defects, and defect extraction Defect impact modeling and yield improvement techniques Physical design and reliability DFM tools and methodologies

VLSI Design and Test

17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Proceedings

Author: Manoj Singh Gaur

Publisher: Springer

ISBN:

Category: Computers

Page: 388

View: 487

This book constitutes the refereed proceedings of the 17th International Symposium on VLSI Design and Test, VDAT 2013, held in Jaipur, India, in July 2013. The 44 papers presented were carefully reviewed and selected from 162 submissions. The papers discuss the frontiers of design and test of VLSI components, circuits and systems. They are organized in topical sections on VLSI design, testing and verification, embedded systems, emerging technology.

Handbook of Nanoscale Optics and Electronics

Author:

Publisher: Academic Press

ISBN:

Category: Technology & Engineering

Page: 560

View: 927

With the increasing demand for smaller, faster, and more highly integrated optical and electronic devices, as well as extremely sensitive detectors for biomedical and environmental applications, a field called nano-optics or nano-photonics/electronics is emerging – studying the many promising optical properties of nanostructures. Like nanotechnology itself, it is a rapidly evolving and changing field – but because of strong research activity in optical communication and related devices, combined with the intensive work on nanotechnology, nano-optics is shaping up fast to be a field with a promising future. This book serves as a one-stop review of modern nano-optical/photonic and nano-electronic techniques, applications, and developments. Provides overview of the field of Nano-optics/photonics and electronics, detailing practical examples of photonic technology in a wide range of applications Discusses photonic systems and devices with mathematical rigor precise enough for design purposes A one-stop review of modern nano-optical/photonic and nano-electronic techniques, applications, and developments.

VLSI

Author: Zhongfeng Wang

Publisher: BoD – Books on Demand

ISBN:

Category: Technology & Engineering

Page: 466

View: 366

The process of Integrated Circuits (IC) started its era of VLSI (Very Large Scale Integration) in 1970’s when thousands of transistors were integrated into one single chip. Nowadays we are able to integrate more than a billion transistors on a single chip. However, the term “VLSI” is still being used, though there was some effort to coin a new term ULSI (Ultra-Large Scale Integration) for fine distinctions many years ago. VLSI technology has brought tremendous benefits to our everyday life since its occurrence. VLSI circuits are used everywhere, real applications include microprocessors in a personal computer or workstation, chips in a graphic card, digital camera or camcorder, chips in a cell phone or a portable computing device, and embedded processors in an automobile, et al. VLSI covers many phases of design and fabrication of integrated circuits. For a commercial chip design, it involves system definition, VLSI architecture design and optimization, RTL (register transfer language) coding, (pre- and post-synthesis) simulation and verification, synthesis, place and route, timing analyses and timing closure, and multi-step semiconductor device fabrication including wafer processing, die preparation, IC packaging and testing, et al. As the process technology scales down, hundreds or even thousands of millions of transistors are integrated into one single chip. Hence, more and more complicated systems can be integrated into a single chip, the so-called System-on-chip (SoC), which brings to VLSI engineers ever increasingly challenges to master techniques in various phases of VLSI design. For modern SoC design, practical applications are usually speed hungry. For instance, Ethernet standard has evolved from 10Mbps to 10Gbps. Now the specification for 100Mbps Ethernet is on the way. On the other hand, with the popularity of wireless and portable computing devices, low power consumption has become extremely critical. To meet these contradicting requirements, VLSI designers have to perform optimizations at all levels of design. This book is intended to cover a wide range of VLSI design topics. The book can be roughly partitioned into four parts. Part I is mainly focused on algorithmic level and architectural level VLSI design and optimization for image and video signal processing systems. Part II addresses VLSI design optimizations for cryptography and error correction coding. Part III discusses general SoC design techniques as well as other application-specific VLSI design optimizations. The last part will cover generic nano-scale circuit-level design techniques.

VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability

24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers

Author: Thomas Hollstein

Publisher: Springer

ISBN:

Category: Computers

Page: 233

View: 433

This book contains extended and revised versions of the best papers presented at the 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, held in Tallinn, Estonia, in September 2016. The 11 papers included in the book were carefully reviewed and selected from the 36 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the latest scientific and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) Design.

Systems Engineering for Microscale and Nanoscale Technologies

Author: M. Ann Garrison Darrin

Publisher: CRC Press

ISBN:

Category: Technology & Engineering

Page: 592

View: 543

To realize the full potential of micro- and nanoscale devices in system building, it is critical to develop systems engineering methodologies that successfully integrate stand-alone, small-scale technologies that can effectively interface with the macro world. So how do we accomplish this?Systems Engineering for Microscale and Nanoscale Technologie

Design and Modeling of Low Power VLSI Systems

Author: Sharma, Manoj

Publisher: IGI Global

ISBN:

Category: Technology & Engineering

Page: 386

View: 206

Very Large Scale Integration (VLSI) Systems refer to the latest development in computer microchips which are created by integrating hundreds of thousands of transistors into one chip. Emerging research in this area has the potential to uncover further applications for VSLI technologies in addition to system advancements. Design and Modeling of Low Power VLSI Systems analyzes various traditional and modern low power techniques for integrated circuit design in addition to the limiting factors of existing techniques and methods for optimization. Through a research-based discussion of the technicalities involved in the VLSI hardware development process cycle, this book is a useful resource for researchers, engineers, and graduate-level students in computer science and engineering.

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits

Author: Saraju P. Mohanty

Publisher: Springer

ISBN:

Category: Technology & Engineering

Page: 302

View: 693

This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.

Embedded Memories for Nano-Scale VLSIs

Author: Kevin Zhang

Publisher: Springer Science & Business Media

ISBN:

Category: Technology & Engineering

Page: 400

View: 136

Kevin Zhang Advancement of semiconductor technology has driven the rapid growth of very large scale integrated (VLSI) systems for increasingly broad applications, incl- ing high-end and mobile computing, consumer electronics such as 3D gaming, multi-function or smart phone, and various set-top players and ubiquitous sensor and medical devices. To meet the increasing demand for higher performance and lower power consumption in many different system applications, it is often required to have a large amount of on-die or embedded memory to support the need of data bandwidth in a system. The varieties of embedded memory in a given system have alsobecome increasingly more complex, ranging fromstatictodynamic and volatile to nonvolatile. Among embedded memories, six-transistor (6T)-based static random access memory (SRAM) continues to play a pivotal role in nearly all VLSI systems due to its superior speed and full compatibility with logic process technology. But as the technology scaling continues, SRAM design is facing severe challenge in mainta- ing suf?cient cell stability margin under relentless area scaling. Meanwhile, rapid expansion in mobile application, including new emerging application in sensor and medical devices, requires far more aggressive voltage scaling to meet very str- gent power constraint. Many innovative circuit topologies and techniques have been extensively explored in recent years to address these challenges.

Event-Based Control and Signal Processing

Author: Marek Miskowicz

Publisher: CRC Press

ISBN:

Category: Technology & Engineering

Page: 558

View: 615

Event-based systems are a class of reactive systems deployed in a wide spectrum of engineering disciplines including control, communication, signal processing, and electronic instrumentation. Activities in event-based systems are triggered in response to events usually representing a significant change of the state of controlled or monitored physical variables. Event-based systems adopt a model of calls for resources only if it is necessary, and therefore, they are characterized by efficient utilization of communication bandwidth, computation capability, and energy budget. Currently, the economical use of constrained technical resources is a critical issue in various application domains because many systems become increasingly networked, wireless, and spatially distributed. Event-Based Control and Signal Processing examines the event-based paradigm in control, communication, and signal processing, with a focus on implementation in networked sensor and control systems. Featuring 23 chapters contributed by more than 60 leading researchers from around the world, this book covers: Methods of analysis and design of event-based control and signal processing Event-driven control and optimization of hybrid systems Decentralized event-triggered control Periodic event-triggered control Model-based event-triggered control and event-triggered generalized predictive control Event-based intermittent control in man and machine Event-based PID controllers Event-based state estimation Self-triggered and team-triggered control Event-triggered and time-triggered real-time architectures for embedded systems Event-based continuous-time signal acquisition and DSP Statistical event-based signal processing in distributed detection and estimation Asynchronous spike event coding technique with address event representation Event-based processing of non-stationary signals Event-based digital (FIR and IIR) filters Event-based local bandwidth estimation and signal reconstruction Event-Based Control and Signal Processing is the first extensive study on both event-based control and event-based signal processing, presenting scientific contributions at the cutting edge of modern science and engineering.