Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base. LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers.
This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.
According to Moore's law, the number of transistors on integrated circuits (ICs) double approximately every two years. Over the years, this growth in number of transistors has reached to billions of transistors per IC, operating at very high frequencies. However, there are many factors limiting this growth rate including power consumption of high-density high-speed integrated circuits. Various techniques have evolved offering reduction in dynamic power consumption and leakage power. Traditional methods like use of power efficient circuits, parallelism in micro-architectures, along with nontraditional methods such as clock gating, variable supply voltage and frequency scaling are becoming significantly important in lowering dynamic power consumption. The leakage power, which has become more significant in the recent high-density designs, can be reduced by minimizing usage of low threshold voltage cells, adding power gating, back biasing, reducing oxide thickness, and using new devices such as FINFET's. Design engineers have to consider clock and power gating techniques up front in the design cycle in today's multi-threshold, multi-oxide, multi-voltage and multi-clock devices. Understanding and implementing power intent at register transfer level (RTL), netlist and PG netlist stages requires additional design verification efforts. In this project, several power reduction and management techniques were studied and applied to an existing System on Chip (SoC) system consisting of an ARM processor, an Ethernet controller, and a DDR controller. Clock and Multi VDD power gating were considered as primary techniques for achieving power reduction. Power intent was created as per the IEEE 1801-2009 Unified Power Format standard. Open source Verilog model of the SoC ARM processor was used as a reference model, along with Synopsys® 90 nm cell library. Synopsys® Electronic Design Automation (EDA) tools were utilized in carrying out simulation, synthesis, and power analysis phases of the project. In addition to implementation of low-power RTL design techniques, use of clock gating, power gating, multi-voltage design partition and multi-threshold voltage cells showed significant improvement in power consumption of the System on Chip (SoC) system used in this work. By considering design issues and verification requirements of these techniques, we developed a power-aware SoC design flow. This enhanced methodology presents a unique approach for effectively incorporating low-power techniques early in the design phase.
17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings
Author: Nadine Azemard
Publisher: Springer Science & Business Media
Annotation This book constitutes the refereed proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2007, held in Gothenburg, Sweden, in September 2007. The 36 revised full papers and 19 revised poster papers presented together with the abstracts of 3 key notes and 2 industrial papers were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on high-level design, low power design techniques, low power analog circuits, statistical static timing analysis, power modeling and optimization, low power routing optimization, security and asynchronous design, low power applications, modeling and optimization, low power techniques and applications, as well as design challenges in real-life projects.
Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits (digital and analog), systems on chip, microelectronic systems, wirelessly networked systems of computational nodes and so on. In addition to providing an in-depth analysis of the sources of power dissipation in VLSI circuits and systems and the technology and design trends, this book provides a myriad of state-of-the-art approaches to power optimization and control. The different chapters of Power Aware Design Methodologies have been written by leading researchers and experts in their respective areas. Contributions are from both academia and industry. The contributors have reported the various technologies, methodologies, and techniques in such a way that they are understandable and useful.
21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011, Proceedings
Author: Jose L. Ayala
This book constitutes the refereed proceedings of the 21st International Conference on Integrated Circuit and System Design, PATMOS 2011, held in Madrid, Spain, in September 2011. The 34 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper feature emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems and focus especially on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization.
Introduction The purpose of this book is to provide insight and intuition into the analog and analog-mixed signal system verification. It is also a journey the author of this book has been through on the way to tackle practical design and verification challenges with state of art analog and mixed signal designs. Motivation for authoring this book The digital design verification skill set is very different than analog design and verification. Traditionally, the analog block level verification is performed by the analog designers, and digital design verification is performed by digital design verification engineer. Lack of cross domain skill set makes it challenging to perform verification at mixed-signal level. Hence, either analog designer engineer should learn advanced digital verification techniques or digital design verification engineer embrace analog verification to become analog-mixed signal verification engineer. This book is written keeping this new trend in mind, hence it covers digital design fundamentals, digital design verification as well as analog design fundamentals, and analog performance verification. Organization of this book Keeping the readers of analog verification or digital design verification background in mind, the book has first 5 chapters focused on the fundamentals of the analog design, digital design, and its verification. Chapter 6 and chapter 7 focuses on the analog-mixed signal design verification and behavioral modeling respectively. Chapter 8 is dedicated to the low power verification techniques. Chapter 1: Introduction to Analog Mixed Signal Verification This chapter discusses about the evolution of the verification methodologies, history of analog-mixed signal designs, applications, and future trends. Chapter 2: Analog Design Fundamentals The purpose of this chapter is to give an overview of the analog design fundamentals for digital design background engineers. Major focus is given on analog behavior, design criteria and their concept rather than design themselves, such as voltage/current reference, some of the basic key analog design properties such as gain, band width, basics of jitter, eye diagram, etc. Chapter 3: Digital Design Fundamentals In this chapter, we explain digital design flow, combinational and sequential logic design fundamentals, design for testability, concepts of timing, and timing verification. Chapter 4: Analog Verification This chapter focuses on analog performance verification and functional verification under the context of mixed signal design hierarchical verification rather than the detail performance analysis of the designs themselves. Chapter 5: Digital Design Verification This chapter explains the tools and methodologies that are evolved over the period that are predicated on predictable quality and verification efficiency. The chapter contains the sections on the coverage driven verification (CDV) methodology, assertion based verification (ABV) methodology, and overview of the CDV using Open Verification Methodology (OVM). Chapter 6: Analog-Mixed Signal Verification This chapter discusses about the AMS verification phases, choosing the right abstraction of DUT for a given verification challenge, AMS verification planning, testplanning for AMS design verification, and testbench development with re-use in mind. Chapter 7: Analog Behavioral Modeling This chapter explains about the applications of analog behavioral models, modeling methodology, simple examples of various analog behavioral modeling styles, selection of accuracy level of the models based on the verification plan, model verification, and signoff. Chapter 8: Low Power Verification The purpose of this chapter is to explain the low power design verification challenges, key low power design elements, low power design techniques, low power design and verification cycle, testplanning for low power design verification, power aware digital, and AMS simulations.
A Comprehensive Guide to Technologies and Methodologies
Author: Ashok B. Mehta
Category: Technology & Engineering
This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.
This book contains all the topics of importance to the low power designer. It first lays the foundation and then goes on to detail the design process. The book also discusses such special topics as power management and modal design, ultra low power, and low power design methodology and flows. In addition, coverage includes projections of the future and case studies.
This book brings together a selection of the best papers from the twentiethedition of the Forum on specification and Design Languages Conference (FDL), which took place on September 18-20, 2017, in Verona, Italy. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems. Covers modeling and verification methodologies targeting digital and analog systems; Addresses firmware development and validation; Targets both functional and non-functional properties; Includes descriptions of methods for reliable system design.
All the design and development inspiration and direction an electronics engineer needs in one blockbuster book! John Donovan, Editor-in Chief, Portable Design has selected the very best electronic design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of electronic design from design fundamentals to low-power approaches with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving electronic design problems and how to successfully apply theory to actual design tasks. The material has been selected for its timelessness as well as for its relevance to contemporary electronic design issues. Contents: Chapter 1 System Resource Partitioning and Code Optimization Chapter 2 Low Power Design Techniques, Design Methodology, and Tools Chapter 3 System-Level Approach to Energy Conservation Chapter 4 Radio Communication Basics Chapter 5 Applications and Technologies Chapter 6 RF Design Tools Chapter 7 On Memory Systems and Their Design Chapter 8 Storage in Mobile Consumer Electronics Devices Chapter 9 Analog Low-Pass Filters Chapter 10 Class A Amplifiers Chapter 11 MPEG-4 and H.264 Chapter 12 Liquid Crystal Displays *Hand-picked content selected by John Donovan, Editor-in Chief, Portable Design *Proven best design practices for low-power, storage, and streamlined development *Case histories and design examples get you off and running on your current project
Presenting a comprehensive overview of the design automation algorithms, tools, and methodologies used to design integrated circuits, the Electronic Design Automation for Integrated Circuits Handbook is available in two volumes. The first volume, EDA for IC System Design, Verification, and Testing, thoroughly examines system-level design, microarchitectural design, logical verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for IC designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. Save on the complete set.
Second International Workshop, PACS 2002 Cambridge, MA, USA, February 2, 2002, Revised Papers
Author: PACS 2002
Publisher: Springer Science & Business Media
This book constitutes the thoroughly refereed post-proceedings of the Second International Workshop on Power-Aware Computer Systems, PACS 2002, held in Cambridge, MA, USA, in February 2002. The 13 revised full papers presented were carefully selected for inclusion in the book during two rounds of reviewing and revision. The papers are organized in topical sections on power-aware architecture and microarchitecture, power-aware real-time systems, power modeling and monitoring, and power-aware operating systems and compilers.
11th International Haifa Verification Conference, HVC 2015, Haifa, Israel, November 17-19, 2015, Proceedings
Author: Nir Piterman
This book constitutes the refereed proceedings of the 11th International Haifa Verification Conference, HVC 2015, held in Haifa, Israel, in November 2015. The 17 revised full papers and 4 invited talks presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on hybrid systems; tools; verification of robotics; symbolic execution; model checking; timed systems; SAT solving; multi domain verification; and synthesis.
Explains how to use low power design in an automated design flow, and examine the design time and performance trade-offs Includes the latest tools and techniques for low power design applied in an ASIC design flow Focuses on low power in an automated design methodology, a much neglected area
Abstract: A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power management architecture. The method supports incremental refinement of power intent specifications required for IP-based designflows. Keywords: corruption semantics, IEEE 1801, interface specification, IP reuse, isolation, level-shifting, power-aware design, power domains, power intent, power modes, power states, progressive design refinement, retention, retention strategies.