This book walks the reader through the next step in the evolution of NAND flash memory technology, namely the development of 3D flash memories, in which multiple layers of memory cells are grown within the same piece of silicon. It describes their working principles, device architectures, fabrication techniques and practical implementations, and highlights why 3D flash is a brand new technology. After reviewing market trends for both NAND and solid state drives (SSDs), the book digs into the details of the flash memory cell itself, covering both floating gate and emerging charge trap technologies. There is a plethora of different materials and vertical integration schemes out there. New memory cells, new materials, new architectures (3D Stacked, BiCS and P-BiCS, 3D FG, 3D VG, 3D advanced architectures); basically, each NAND manufacturer has its own solution. Chapter 3 to chapter 7 offer a broad overview of how 3D can materialize. The 3D wave is impacting emerging memories as well and chapter 8 covers 3D RRAM (resistive RAM) crosspoint arrays. Visualizing 3D structures can be a challenge for the human brain: this is way all these chapters contain a lot of bird’s-eye views and cross sections along the 3 axes. The second part of the book is devoted to other important aspects, such as advanced packaging technology (i.e. TSV in chapter 9) and error correction codes, which have been leveraged to improve flash reliability for decades. Chapter 10 describes the evolution from legacy BCH to the most recent LDPC codes, while chapter 11 deals with some of the most recent advancements in the ECC field. Last but not least, chapter 12 looks at 3D flash memories from a system perspective. Is 14nm the last step for planar cells? Can 100 layers be integrated within the same piece of silicon? Is 4 bit/cell possible with 3D? Will 3D be reliable enough for enterprise and datacenter applications? These are some of the questions that this book helps answering by providing insights into 3D flash memory design, process technology and applications.
Offers a comprehensive overview of NAND flash memories, with insights into NAND history, technology, challenges, evolutions, and perspectives Describes new program disturb issues, data retention, power consumption, and possible solutions for the challenges of 3D NAND flash memory Written by an authority in NAND flash memory technology, with over 25 years’ experience
The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising Moore-like exponential growth sustainable through to the 2030s.
This cutting-edge book on off-chip technologies puts the hottest breakthroughs in high-density compliant electrical interconnects, nanophotonics, and microfluidics at your fingertips, integrating the full range of mathematics, physics, and technology issues together in a single comprehensive source. You get full details on state-of-the-art I/O interconnects and packaging, including mechanically compliant I/O approaches, fabrication, and assembly, followed by the latest advances and applications in power delivery design, analysis, and modeling. The book explores interconnect structures, materials, and packages for achieving high-bandwidth off-chip electrical communication, including optical interconnects and chip-to-chip signaling approaches, and brings you up to speed on CMOS integrated optical devices, 3D integration, wafer stacking technology, and through-wafer interconnects.
The large scale integration and planar scaling of individualsystem chips is reaching an expensive limit. If individual chipsnow, and later terrabyte memory blocks, memory macros, andprocessing cores, can be tightly linked in optimally designed andprocessed small footprint vertical stacks, then performance can beincreased, power reduced and cost contained. This book reviews forthe electronics industry engineer, professional and student thecritical areas of development for 3D vertical memory chipsincluding: gate-all-around and junction-less nanowire memories,stacked thin film and double gate memories, terrabit verticalchannel and vertical gate stacked NAND flash, large scale stackingof Resistance RAM cross-point arrays, and 2.5D/3D stacking ofmemory and processor chips with through-silicon-via connections now and remote links later. Key features: Presents a review of the status and trends in 3-dimensionalvertical memory chip technologies. Extensively reviews advanced vertical memory chip technologyand development Explores technology process routes and 3D chip integration in asingle reference
Economic Principles of Performance, Cost and Reliability Optimization
Author: Detlev Richter
Publisher: Springer Science & Business Media
Category: Technology & Engineering
The subject of this book is to introduce a model-based quantitative performance indicator methodology applicable for performance, cost and reliability optimization of non-volatile memories. The complex example of flash memories is used to introduce and apply the methodology. It has been developed by the author based on an industrial 2-bit to 4-bit per cell flash development project. For the first time, design and cost aspects of 3D integration of flash memory are treated in this book. Cell, array, performance and reliability effects of flash memories are introduced and analyzed. Key performance parameters are derived to handle the flash complexity. A performance and array memory model is developed and a set of performance indicators characterizing architecture, cost and durability is defined. Flash memories are selected to apply the Performance Indicator Methodology to quantify design and technology innovation. A graphical representation based on trend lines is introduced to support a requirement based product development process. The Performance Indicator methodology is applied to demonstrate the importance of hidden memory parameters for a successful product and system development roadmap. Flash Memories offers an opportunity to enhance your understanding of product development key topics such as: · Reliability optimization of flash memories is all about threshold voltage margin understanding and definition; · Product performance parameter are analyzed in-depth in all aspects in relation to the threshold voltage operation window; · Technical characteristics are translated into quantitative performance indicators; · Performance indicators are applied to identify and quantify product and technology innovation within adjacent areas to fulfill the application requirements with an overall cost optimized solution; · Cost, density, performance and durability values are combined into a common factor – performance indicator - which fulfills the application requirements
Adobe Flash is one of today's most popular game-development applications, giving programmers the power to create high-speed, hardware-driven 2D and 3D games and applications across many platforms and throughout the broad landscape of social network gaming. And with the significantly improved performance of Flash-created games on devices such as the iPhone, iPad, and Android mobiles, the latest versions of Flash Pro are capable of delivering powerful games into the world of mobile technology. If you're a developer who already knows the basics of Flash, and you're looking for tips and techniques that will help you debug your ActionScript 3.0 code, optimize your games, and test their efficiency, this is the book for you. For more than a decade, Adobe Certified Expert Keith Gladstien has helped Flash users solve thousands of programming-related problems on the Adobe ActionScript and Flash forums. Now, with the help of Keith's expertise collected in FLASH GAME DEVELOPMENT IN A SOCIAL, MOBILE, AND 3D WORLD, you will sharpen and perfect your Flash skills, and you'll find the help you need to solve every ActionScript problem you're likely to encounter. To simplify things for you, the book's companion website includes nearly all of the code that appears in the book. Start refining your skills and building your confidence with Adobe Flash and ActionScript today, with FLASH GAME DEVELOPMENT IN A SOCIAL, MOBILE, AND 3D WORLD.
Digital photography, MP3, digital video, etc. make extensive use of NAND-based Flash cards as storage media. To realize how much NAND Flash memories pervade every aspect of our life, just imagine how our recent habits would change if the NAND memories suddenly disappeared. To take a picture it would be necessary to find a film (as well as a traditional camera...), disks or even magnetic tapes would be used to record a video or to listen a song, and a cellular phone would return to be a simple mean of communication rather than a multimedia console. The development of NAND Flash memories will not be set down on the mere evolution of personal entertainment systems since a new killer application can trigger a further success: the replacement of Hard Disk Drives (HDDs) with Solid State Drives (SSDs). SSD is made up by a microcontroller and several NANDs. As NAND is the technology driver for IC circuits, Flash designers and technologists have to deal with a lot of challenges. Therefore, SSD (system) developers must understand Flash technology in order to exploit its benefits and countermeasure its weaknesses. Inside NAND Flash Memories is a comprehensive guide of the NAND world: from circuits design (analog and digital) to Flash reliability (including radiation effects), from testing issues to high-performance (DDR) interface, from error correction codes to NAND applications like Flash cards and SSDs.
NAND flash memories are ubiquitous in their use as portable storage media in cellphones, cameras, music players, and other portable electronic devices. The NAND flash memory device, consisting of a floating-gate transistor cell, is the most aggressively scaled electronic device, as evidenced by ever-increasing memory capacities. In this work, we will examine possible problems arising from continued scaling of these structures, and discuss novel solutions to overcome them. Firstly, we investigate scaling of the conventional poly-silicon floating-gate, aimed at reducing cell-to-cell interference. We experimentally delineate a new reliability concern for the first time, with programming current through ultra-thin poly-silicon floating-gates becoming increasingly ballistic. We also experimentally demonstrate doping-related issues in the poly-silicon floating-gate. We then apply a novel metal-based floating-gate cell for the first time, designed to overcome the problems discussed above. We explore factors that influence the choice of metal, and demonstrate excellent functionality in ultra-thin metal floating-gate cells scaled down to 3 nm TiN floating-gate thickness, thus greatly reducing cell-to-cell interference. Finally, in order to facilitate continued scaling of the control dielectric, we explore replacement of the conventional silicon oxide-nitride dielectric with high-k dielectric materials. We integrate poly-silicon and metal floating-gate cells with Al2O3 high-k control dielectric. Further, we establish that a deeper work-function control gate is helpful in reducing gate-injection. Combining ultra-thin metal floating-gate, high-k control dielectric and deep work-function control gate, we enable the planar floating-gate cell as a scalable candidate.
This book introduces simulation tools and strategies for complex systems of solid-state-drives (SSDs) which consist of a flash multi-core microcontroller plus NAND flash memories. It provides a broad overview of the most popular simulation tools, with special focus on open source solutions. VSSIM, NANDFlashSim and DiskSim are benchmarked against performances of real SSDs under different traffic workloads. PROs and CONs of each simulator are analyzed, and it is clearly indicated which kind of answers each of them can give and at a what price. It is explained, that speed and precision do not go hand in hand, and it is important to understand when to simulate what, and with which tool. Being able to simulate SSD’s performances is mandatory to meet time-to-market, together with product cost and quality. Over the last few years the authors developed an advanced simulator named “SSDExplorer” which has been used to evaluate multiple phenomena with great accuracy, from QoS (Quality Of Service) to Read Retry, from LDPC Soft Information to power, from Flash aging to FTL. SSD simulators are also addressed in a broader context in this book, i.e. the analysis of what happens when SSDs are connected to the OS (Operating System) and to the end-user application (for example, a database search). The authors walk the reader through the full simulation flow of a real system-level by combining SSD Explorer with the QEMU virtual platform. The reader will be impressed by the level of know-how and the combination of models that such simulations are asking for.